The present invention relates to a semiconductor integrated circuit such as a micro-processor, and a debugging system for program development supports.
In recent years, demand of shortening the development cycle of the system which mounts a micro-processor is increasing, and a debugging support function which supports program development is frequently provided in the micro-processor. Especially the trace information output function that outputs externally trace information, such as a flow of the program which the micro-processor has executed, and updating of data, is an important function for supporting the program development. The trace information supplied externally is taken into a debugging device coupled to the micro-processor and utilized for the analysis of execution of a program. However, the trace information is increasing in quantity due to improvement in the speed of the micro-processor, and it is not easy to take out the increasing trace information to the exterior of the micro-processor. In order to take out the trace information to the exterior of the micro-processor, a pin must be provided in the micro-processor. Although the trace information output bandwidth can be improved by the increase in the number of the pin, and by raising the frequency of an output circuit, the increase in the number of the pin and raising the frequency of the output circuit lead to increase of the cost of the micro-processor. Therefore, there are limitations in improving the trace information output bandwidth. Although the trace information is stored in a memory inside the micro-processor, the memory also has a limitation in capacity. The technology of a branch trace is known as an example of the trace information output for reproducing the flow of processing of a program (for example, refer to Patent Document 1). In the technique, when a branch occurs in a program execution process, a branch destination address and a branch source address are outputted externally. According to the method, it is possible to reproduce the program execution flow without outputting all the instruction execution processes, suppressing the output quantity of the trace information. In this method, the information on the same branch trace is repeatedly outputted for the loop part in a program. To cope with the issue, Patent Document 2 discloses a technology which provides a loop decision circuit. The loop decision circuit is able to suppress the trace output and to reduce trace information by detecting that an instruction is under execution inside of a loop, and to control the start of trace information extraction by detecting that the instruction is under execution outside the loop. Patent Document 3 discloses another technology which detects a loop and controls to delete a repetitive middle part of the loop, leaving only the last loop.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 8(1996)-185336)
[Patent Document 2] Japanese Unexamined Patent Publication No. 2001-5689
[Patent Document 3] Japanese Unexamined Patent Publication No. Hei 11(1999)-219293